As semiconductor technologies advance, radio frequency (RF) applications require increasing standards of linearity in the transmission and amplification of high frequency signals. For example, applications such as RF switching, attenuation and antenna tuning require switch branches capable of transmitting high-power RF signals in the 0.5 GHz to 6 GHz range with a high degree of linearity. To accommodate high power levels, conventional approaches include stacking several low voltage NMOS transistors drain-to-source while isolating the gate and body nodes of each of the transistors using high value resistors.
However, in practice, isolation of the body node in silicon-on-insulator (SOI) technologies is challenging due to the formation of a parasitic conduction layer (PCL) at the interface between the base oxide layer and the substrate. Such a PCL may be neutralized by employing expensive manufacturing techniques such as polysilicon passivated substrates. However, even with such manufacturing techniques, further improvement in switch branch linearity will result in better end-system performance.